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1 ? fn6699.1 isl54405 cd/mp3 quality stereo 2:1 multiplexer with click and pop elimination the intersil isl54405 is a single supply, bidirectional, dual single-pole/double-throw (spdt) ultra low distortion, high off-isolation analog switch th at can pass analog signals that are positive and negative with re spect to ground. it is primarily targeted at consumer and pr ofessional audio switching applications such as computer sound cards and home theater products. the inpu ts can accommodate ground referenced signals up to 2v rms while operating from a single 3.3v or 5v dc supply. the digital logic inputs are 1.8v logic-compatible when using a single 3.3v or 5v supply. it can be used in both ac or dc coupled ground referenced applications. the isl54405 features a soft-s witch feature and click/pop circuitry at each signal pin th at eliminates clicks and pops associated with power-up/down co nditions of the preceding amplifier outputs. with -106db thd+n performance with a 2v rms signal into 20k load, superior signal muting, high psrr and very flat frequency response the isl54405 meets the exacting requirements of consumer and professional audio engineers. the isl54405 is available in 16 ld tssop, 16 ld 3mmx3mm tqfn, and 16 ld 2.6mmx1.8mm tqfn packages. its specified for operation over t he -40c to +85c temperature range. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? features ? clickless audio switching ?2v rms signal switching from 3.3v or 5v supply ? -106db thd+n into 20k load @ 2v rms ? -108db thd+n into 32 load @ 3.9mw ? signal to noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >124dbv ? 0.01db insertion loss at 1khz, 20k load ? 0.007db gain variation 20hz to 20khz ? 125db signal muting into 20k load ?90db psrr 20hz to 20khz ? single supply operation . . . . . . . . . . . . . . . . . . . . 3.3v or 5v ? available in 16 ld tssop, 16 ld tqfn, and 16 ld tqfn ? pb-free (rohs compliant) applications ? computer sound cards ? home theater audio products ? sacd/dvd audio ? dvd player audio output switching ? headsets for mp3/cellphone switching ? hi-fi audio switching application block diagram table 1. features at a glance isl54405 number of switches 2 switch type spdt or 2 to 1 mux insertion loss 0.01db thd+n, 2v rms , 20k load -106db off-isolation (mute) 125db packages 16 ld tssop, 16 ld 3x3 tqfn, 16 ld 2.6x1.8 tqfn logic isl54405 sel mute l r l1 l2 r1 r2 cap_ss vdd 5v_supply for 5v operation connect the 5v_s upply pin to 5v and float the vdd pin. for 3.3v operation connect the vdd pin to 3.3v and float gnd ac/dc the 5v_supply pin. dir_sel control and click/pop data sheet june 5, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6699.1 june 5, 2008 pinouts (note 1) isl54405 (16 ld tqfn) top view isl54405 (16 ld tqfn) top view isl54405 (16 ld tssop) top view note: 1. see page 1 for isl54405 block diagram. 1 3 4 15 mute l r sel ac/dc 5v_supply vdd cap_ss 16 14 13 2 12 10 9 11 6 578 l1 l2 r1 r2 gnd dir_sel gnd gnd 1 3 4 15 mute l r sel ac/dc 5v_supply vdd cap_ss 16 14 13 2 12 10 9 11 6 578 l1 l2 r1 r2 gnd dir_sel gnd gnd 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 5v_supply ac/dc mute l r sel dir_sel gnd vdd l1 l2 r1 r2 gnd gnd cap_ss isl54405
3 fn6699.1 june 5, 2008 truth table inputs outputs ac/dc dir mute sel l1, r1 l2, r2 com (l,r) c/p shunts l1, r1 c/p shunts l2, r2 c/p shunts 0 x 0 0 on off off off off 0 x 0 1 off on off off off 0 x 1 x off off off off off 1000onoffoffoffon 1001offonoffonoff 1 0 1 x off off off on on 1100onoffoffoffoff 1101offonoffoffoff 1 1 1 x off off on off off note: mute, ac/dc, dir: logic ?0? 0.5v, logic ?1? 1.4v or float with a 3.3v supply or 5v supply. sel: logic ?0? 0.5v, logic ?1? 1.4v with a 3.3v supply or 5v supply. x = don?t care pin descriptions pin function vdd system power supply pin (+3v to +3.6v) (float pin for 5v applications) 5v_supply 5v supply pin (+4.5v to +5.5v) (float pin for 3.3v applications) gnd ground connection cap_ss soft-start capacitor pin mute signal mute control pin sel input select control pin ac/dc ac/dc select control pin dir_sel direction select control pin r analog switch common pin l analog switch common pin l2, r2 analog switch normally open pin l1, r1 analog switch normally closed pin pin descriptions (continued) pin function ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # isl54405ivz (note 2) 54405 ivz -40 to +85 16 ld tssop m16.173 isl54405ivz-t* (note 2) 54405 ivz -40 to +85 16 ld tssop m16.173 ISL54405IRTZ (note 2) 05tz -40 to +85 16 ld 3x3 tqfn l16.3x3a ISL54405IRTZ-t* (note 2) 05tz -40 to +85 16 ld 3x3 tqfn l16.3x3a isl54405iruz-t* (note 3) gad -40 to+ 85 16 ld tqfn l16.2.6x1.8a *please refer to tb347 for detai ls on reel specifications. notes: 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations. intersil pb-free products are ms l classified at pb-free peak reflow temperatures that meet or exceed the pb-free re quirements of ipc/jedec j std-020. 3. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersi l pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020 isl54405
4 fn6699.1 june 5, 2008 absolute maximum rati ngs thermal information vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 4.0v 5v_supply to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v input voltages sel, mute, ac/dc, dir_sel (note 4) . . -0.3 to ((v dd ) + 0.3v) l1, l2, r1, r2 (note 4) . . . . . . . . . . . . . . . . -3.1 to ((v dd ) + 0.3v output voltages r, l (note 4). . . . . . . . . . . . . . . . . . . . . . . . -3.1 to ((v dd ) + 0.3v) continuous current l1, l2, r1, r2 or l, r . . . . . . . . . . . . . 300ma peak current l1, l2, r1, r2 or l, r (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . 500ma esd rating: human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .> 5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kv thermal resistance (typical) ja (c/w) jc (c/w) 16 ld tssop package (note 5) . . . . . 150 n/a 16 ld tqfn package (notes 6, 7). . . . 75 11 16 ld tqfn package (note 6) . . . . . 93 n/a maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. signals on l1, l2, r1 , r2, mute, sel, ac/dc, dir_sel, r, and l exceeding v dd or gnd by specified amount are clamped. limit current to maximum current ratings. 5. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 6. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications - 3.3v supply test conditions: v dd = +3.0v to +3.6v, gnd = 0v, v dir_sel = v ac/dc = gnd, v 5v_supply = float, v signal = 2v rms , r load = 20k , f = 1khz, v selh = v muteh = 1.4v, v sell = v mutel = 0.5v, cap_ss = 0.1f, (note 8), unless otherwise specified. parameter test conditions suppl y tem p (c) min (notes 9, 10) typ max (notes 9, 10) units analog switch characteristics analog signal range, v analog 3.3v, 5v full - 2 - v rms on-resistance, r on v dd = 3.3v, i r or i l = 80ma, v lx or v rx = -2.828v to +2.828v (see figure 4) 3.3v 25 - 1.9 - full - 2.6 - r on matching between channels, r on v dd = 3.3v, i r or i l = 80ma, v lx or v rx = voltage at max r on over -2.828v to +2.828v (note 13) 3.3v 25 - 0.023 - full - 0.045 - r on flatness, r flat(on) v dd = 3.3v, i r or i l = 80ma, v lx or v rx = -2.828v, 0v, +2.828v (note 11) 3.3v 25 - 0.003 0.01 full - 0.009 - l, r, lx, rx pull-down resistance v dd = 3.6v, v lx or v rx = -2.83v, 2.83v, v l or v r = -2.83v, 2.83v, v ac/dc = 0v, v mute = 3.6v, measure current, calculate resistance. 3.6v 25 225 300 375 k full - 345 - k dynamic characteristics thd+n v signal = 2v rms , f = 1khz, a-weighted filter, r load = 20k 3.3v, 5v 25 - -106 - db v signal = 1.9v rms , f = 1khz, a-weighted filter, r load = 20k 25 - -113 - db v signal = 1.8v rms , f = 1khz, a-weighted filter, r load = 20k 25 - -116 - db v signal = 0.707v rms , f = 1khz, a-weighted filter, r load = 32 25 - -100 - db snr f = 20hz to 20khz, a-weighted filter, inputs grounded, r load = 20k or 32 3.3v, 5v 25 - >124 - dbv isl54405
5 fn6699.1 june 5, 2008 insertion loss, g on f = 1khz, r load = 20k 3.3v 25 - 0.01 - db gain vs frequency, g f f = 20hz to 20khz, r load = 20k , reference to g on at 1khz 3.3v 25 - 0.007 - db stereo channel imbalance l1 and r1, l2 and r2 f = 20hz to 20khz, r load = 20k 3.3v 25 - 0.003 - db off-isolation (muting) f = 20hz to 22khz, l = r = 2v rms , r load = 20k , mute = ac/dc = 3.3v, dir_sel = gnd, sel = ?x? 3.3v, 5v 25 - 120 - db f = 20hz to 22khz, l1, r1, l2, r2 = 2v rms , r load = 20k , mute = ac/dc = dir_sel = 3.3v, sel = ?x? 25 - 120 - db f = 20hz to 22khz, v l or v r = 0.7v rms , r load =32 25 - 125 - db crosstalk (channel-to- channel) r l = 20k , f = 20hz to 20khz, v signal =2v rms , signal source impedance = 20 , note: crosstalk is inversely proportional to source impedance. 3.3v 25 - 120 - db r l = 32 , f = 20hz to 20khz, v signal =0.7v rms signal source impedance = 20 , note: crosstalk is inversely proportional to source impedance. 25 - 120 - db psrr f = 1khz, v signal = 100mv rms , inputs grounded 3.3v, 5v 25 - 110 - db f = 20khz, v signal = 100mv rms , inputs grounded 25 - 90 - db bandwidth, -3db r load = 50 3.3v 25 - 230 - mhz on to mute time, t trans-om cap_ss = 0.1f 3.3v 25 - 50 - ns mute to on time, t trans-mo cap_ss = 0.1f (selectable via soft-start capacitor value) 3.3v 25 - 58 - ms turn-on time, t on v dd = 3.3v, v lx or v rx = 1.5v, v mute = 0v, r l = 20k , (see figure 1) 3.3v 25 - 45 - s turn-off time, t off v dd = 3.3v, v lx or v rx = 1.5v, v mute = 0v, r l = 20k , (see figure 1) 3.3v 25 - 50 - ns break-before-make time delay, t d v dd = 3.6v, v lx or v rx = 1.5v, v mute = 0v, r l = 20k , see figure 2 3.6v 25 - 45 - s off-isolation r l = 50 , f = 1mhz, v l or v r = 1v rms , (see figure 3) 3.3v 25 - 100 - db crosstalk (channel-to- channel) r l = 50 , f = 1mhz, v l or v r = 1v rms , (see figure 5) 3.3v 25 - 70 - db lx, rx off capacitance, c off f = 1mhz, v lx or v rx = v l or v r = 0v (see figure 6) 3.3v 25 - 10 - pf l, r on capacitance, c com(on) f = 1mhz, v lx or v rx = v com = 0v (see figure 6) 3.3v 25 - 27 - pf power supply characteristics power supply range, vdd 5v_supply = float 3.3v full 3 - 3.6 v power supply range, 5v_supply v dd = float 5v full 4.5 - 5.5 v electrical specifications - 3.3v supply test conditions: v dd = +3.0v to +3.6v, gnd = 0v, v dir_sel = v ac/dc = gnd, v 5v_supply = float, v signal = 2v rms , r load = 20k , f = 1khz, v selh = v muteh = 1.4v, v sell = v mutel = 0.5v, cap_ss = 0.1f, (note 8), unless otherwise specified. (continued) parameter test conditions suppl y tem p (c) min (notes 9, 10) typ max (notes 9, 10) units isl54405
6 fn6699.1 june 5, 2008 positive supply current, i+ v dd = +3.6v, v mute = 0v, v sel = 0v or v dd 3.6v 25 - 54 65 a full - 59 - a v dd = +3.6v, v mute = v dd , v sel = 0v or v dd 3.6v 25 - 14 18 a 3.6v full - 15 - a v dd = +3.6v, v mute = 0v, v sel = 1.8v 3.6v 25 - 55 65 a 3.6v full - 58 - a digital input characteristics input voltage low, v sell , v mutel 3.3v, 5v full - - 0.5 v input voltage high, v selh , v muteh 3.3v, 5v full 1.4 - - v input current, i selh , i sell v dd = 3.6v, v mute = 0v, v sel = 0v or v dd 3.6v full -0.5 0.01 0.5 a input current, i ac/dcl , i dir_sell v dd = 3.6v, v ac/dc , v dir_sel = 0v, v mute = float, v sel = v dd 3.6v full -1.3 -0.7 0.3 a input current, i ac/dch , i dir_selh v dd = 3.6v, v ac/dc , v dir_sel = v dd , v mute =0v, v sel = 0v 3.6v full -0.5 0.01 0.5 a input current, i mutel v dd = 3.6v, v sel = v dd , v mute = 0v 3.6v full -1.3 -0.7 0.3 a input current, i muteh v dd = 3.6v, v sel = 0v, v mute = v dd 3.6v full -0.5 0.01 0.5 a notes: 8. v in = input voltage to perform proper function. 9. the algebraic convention, whereby the most negative value is a mi nimum and the most positive a maximum, is used in this data sheet. 10. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. te mperature limits established b y characterization and are not production tested. 11. flatness is defined as the difference between maximum and minimum value of on-resis tance at the specified analog signal volt age points. 12. limits established by characterization and are not production tested. 13. r on matching between channels is calculated by subtracting the channel with the highest max r on value from the channel with lowest max r on value. test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit electrical specifications - 3.3v supply test conditions: v dd = +3.0v to +3.6v, gnd = 0v, v dir_sel = v ac/dc = gnd, v 5v_supply = float, v signal = 2v rms , r load = 20k , f = 1khz, v selh = v muteh = 1.4v, v sell = v mutel = 0.5v, cap_ss = 0.1f, (note 8), unless otherwise specified. (continued) parameter test conditions suppl y tem p (c) min (notes 9, 10) typ max (notes 9, 10) units 50% t r < 20ns t f < 20ns t off 90% v dd 0v v lx or v rx 0v t on logic input switch input switch output 90% v out v out v (lx or rx) r l r l r on + ----------------------- - = switch input logic input v out r l c l l or r lx or rx sel gnd v dd c mute isl54405
7 fn6699.1 june 5, 2008 figure 1. switching times figure 2a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 2b. test circuit figure 2. break-before-make time figure 3. off-isolation test circuit figure 4. r on test circuit figure 5. crosstalk test circuit figure 6. capacitance test circuit test circuits and waveforms (continued) 90% v dd 0v t d logic input switch output 0v v out logic input sel r or l r l c l v out lx rx v dd gnd v nx c mute analyzer r l signal generator v dd c 0v or v dd lx or rx l, r sel gnd signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. mute v dd c 0v or v dd lx or rx l, r sel gnd v nx v 1 r on = v 1 /80ma 80ma repeat test for all switches. mute 0v or v dd analyzer v dd c lx or rx signal generator r l gnd sel l, r nc l, r lx or rx signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. mute v dd c gnd lx or rx l, r sel impedance analyzer 0v or v dd repeat test for all switches. mute isl54405
8 fn6699.1 june 5, 2008 sound card ac coupled a pplication block diagrams detailed description the isl54405 is a single supply, bi-directional, dual single pole/double throw (spdt) ultra low distortion, high off-isolation analog switch. it was designed to operate from either a 3.3v or 5v single s upply. when operated with a 3.3v or 5v single supply, the switches can accommodate 2.83v peak (2v rms ) ground reference analog signals. the switch r on flatness across this range is extremely small resulting in excellent thd+n performance (0.0006% with 20k load and 0.0014% with 32 load at 707mv rms ). the t-type configuration of the s witch cells prevents signals from getting through to the output when a switch is in the off-state providing for superior mute performance (>120db) in audio applications. the isl54405 has special circuitry to eliminate click and pops in the speakers during power-up and power-down of the audio codec drivers, during removal and insertion of headphones, and while switching between sources and loads. the isl54405 was designed primarily for consumer and professional audio switching applications such as computer sound cards and home theater products. the ?application block diagrams? on this page show two typical sound card applications. in the upper block diagram the isl54405 is being used to route a single stereo sour ce to either the front or back panel line outs of the computer sound card. in the lower block diagram the isl54405 is being used to multiplex two stereo sources to a single line out of the computer sound card. codec controller 0.1f soft-start l r l1 line out or head-phone jack front panel line out or head-phone jack back panel l2 r1 r2 3.3v float capacitor logic audio logic isl54405 sel mute l r l1 l2 r1 r2 cap_ss vdd 5v_supply gnd ac/dc dir_sel control codec controller 0.1f soft-start l r l1 line out or head-phone jack front panel l2 r1 r2 3.3v float capacitor logic audio isl54405 sel mute l r l1 l2 r1 r2 cap_ss vdd 5v_supply gnd ac/dc dir_sel codec audio and click/pop logic control and click/pop isl54405
9 fn6699.1 june 5, 2008 spdt switch cell archit ecture and performance characteristics the normally open (l 2 , r 2 ) and normally closed (l 1 , r 1 ) of the spdt switches are t-type switches that have a typical r on of 1.9 and an off-isolation of >120db. the low on- resistance (1.9 ) and r on flatness (0.003 ) provide very low insertion loss and minimal distortion to applications that require hi-fidelity signal reproduction. the spdt switch cells have internal charge pumps that allow for signals to swing below ground. they were specifically designed to pass audio signals that are ground referenced and have a swing of 2.828v peak while driving either 10k/20k (receiver) or 32 (headphone) loads. each switch cell incorporates special circuitry to gradually decrease the switch resistance when transitioning from the off-state (high impedance) to the on state (1.9 ). the gradual decrease in the switch resistance provides for a slow ramp of the voltage at the load side of the switch which helps to eliminate click and pops in the speaker by suppressing the transient during switching events. the output voltage ramp time is determined by the capacitor value of the soft-start capacitor connected at the cap_ss pin. with a 0.1f ceramic chip capacitor the ramp time is approximately 4.6v/s. the slow ramping of the signal at the output can be disabled by floating the cap_ss pin. in addition to the slow ramp f eature (soft-start feature) of the in line switches, the part has special click and pop (c/p) shunt circuitry at each of the signal pins (l, r, l 1 , l 2 , r 1 , and r 2 ). a pin?s c/p shunt circuitry is activated or de- activated depending on the logic levels applied at the ac/dc and dir_sel control pins. th is shunt circuitry serves two functions: 1. in an ac coupled application they are activated and directed to the source side of the switch to suppress or eliminate click/pop noise in the speaker load when powering up or down of the audio codec drivers. 2. for superior muting the c/p shunt circuitry is activated and directed to the load side of the switch which gives >120db of off-isolatio n when driving a 10k/20k receiver load with an audio signal in the range of 20hz to 22khz. if the ac/dc pin is driven low, all c/p shunt circuitry at all the signal pins (l, r, l1, r1, l2, and r2) are deactivated and not operable. if the ac/dc pin is driven hi gh then the logic at the dir_sel pin will determine whether the l and r (com) c/p shunt circuitry is activated or the l1, l2, r1, and r2 (nox, ncx) c/p shunt circuitry is activated. when the dir_sel is driven low, the l1, r1, l2, r2 c/p shunt circuitry will be activated while the l and r c/p shunt circuitry will be deactivated. when the dir_sel is driven high the l and r c/p shunt circuitry will be activated while the l1, r1, l2, r2 c/p shunt circuitry will be deactivated. note: shunt circuitry that is activated will be turned on when a switch cell is turned off and will be off when a switch cell is turned on. supply voltage, signal amplitude, grounding the power supply connected at vdd or the 5v_supply pin provides power to the isl54405 part. the isl54405 is a single supply device that was designed to be operated with a 3.3v 10% dc supply connecte d at the vdd pin or a 5v 10% dc supply connected at the 5v_supply pin. it was specifically designed to accept ground referenced 2v rms ( 2.828v peak ) audio signals at its signal pins while driving either 10k/20k receiver loads or 32 headphone loads. when using the part in a 3.3v application the 5v_supply pin should be left floating. a 0.1f decoupling capacitor should be connected from the vdd pin to ground to minimize power supply noise and transients. this capacitor should be located as close to the pin as possible. the part also has a 5v supply pin (5v_supply) to allow it to be used in 5v 10% applications. special circuitry within the device converts the 5v, connected at the 5v_supply pin, too 3.3v to properly power the internal circuitry of the device. when using the part in a 5v application the vdd pin should be left floating. a 0.1f decoupling capacitor should be connected from the 5v_supply pin to ground to minimize power supply noise. this capacitor should be located as close to the pin as possible. grounding of the isl54405 should follow a star configuration (see figure 7). all grounds of the ic should be directly connected to the power supply ground return without cascading to other grounds. th is configuration isolates shunt currents of the click and pop transients from the ic ground and optimizes device performance. mute operation when the mute logic pin is driven high the part will go into the mute state. in the mute st ate all switches of the spdts are open while the t-shunt s witches are closed. in addition any activated click and pop shunt circuitry at the signal pins is turned on. see ?logic control? on page 10 for more details. isl54405 l r mute gnd1 vdd sel +3.3v 0.1f gnd2 gnd3 l1 r1 logic control figure 7. star grounding configuration ac/dc dir_sel l2 r2 isl54405
10 fn6699.1 june 5, 2008 mute to on when the mute pin is driven low the isl54405 will transition to the on-state in the following sequence: 1. all active shunt switches turn-off quickly. 2. the resistance of the switches selected by the sel pin will gradually decrease in resistance. they will decrease from their high off-resistance to their on-resistance of 1.9 . this gradual decrease in resistance will allow for the voltage at the load to increase gradually. the voltage ramp rate at the load is determined by the value of the capacitor connected at the cap_ss pin. see figures 27 and 28 in the ?typical performance curves? beginning on page 13. table 2 indicates how the signal ramp rate at the load changes as you change the cap_ss capacitor value. it also shows how the mute turn-on time is affected. on to mute when the mute pin is driven hi gh the switches will turn off quickly (50ns) and the active shunt switches will turn on quickly. note: there is no gradual ramping of the switch resistance in this direction. off-isolation in the mute state when in the mute state, the level of off-isolation across the audio band is dependent on the signal amplitude, external loading, and location of the activated c/p (click/pop) shunt circuitry. during muting the logic of the isl54405 can be configured to activate the c/p shunt circuitry on the load side of the switch or on the source side of the switch, or deactivated on both sides of the switch. with a 0.707v rms signal driving a 32 headphone load the location of the c/p shunt circui try has little effect on the off-isolation performance (> 12 0db of off-isolation in all configurations). see figure 11 in the ?typical performance curves? beginning on page 13. with a 2v rms signal driving a 20k amplifier load the best off-isolation is achieved by placing the c/p shunt circuitry on the load side of the switch (>120db across the audio band). the off-isolation decreases when placing the c/p shunt circuitry on the source side of the switch (>85db across the audio band). see figure 10 in the ?typical performance curves? beginning on page 13. note: for ac coupled applications when powering up or down of the audio codecs the c/p shunts should be activated on the source side of the switch. see ?click and pop operation? on page 11. when using the switch for muting of the audio signal the c/p shunt circuitry should be de-activated on the source side of the switch and directed to the load side of the switch for best possible off-isolation. logic control the isl54405 has four logic control pins; the ac/dc, dir_sel, mute, and sel. the mute and sel control pins determine the state of the switches. the ac/dc and dir_sel control pins determi ne the location of the c/p (click/pop) shunt circuitry and if it will be active or not. see ?truth table? on page 3. the isl54405 logic is 1.8v cmos compatible (low 0.5v and high 1.4v) over a supply range of 3.0v to 3.6v at the vdd pin or 4.5v to 5.5v at t he 5v_supply pin. this allows control via 1.8v or 3v controller. sel, mute control pins the state of the spdt switch es of the isl54405 device is determined by the voltage at the mute pin and the sel pin. the sel control pin is only active when mute is logic ?0?. the mute has an internal pull-up resistor to the internal 3.3v supply rail and can be dr iven high or tri-stated(floated) by the processor. these pins are 1.8v logic compatible. when powering the part by the vdd pin the logic voltage can be as high as the v dd voltage which is typically 3.3v. when powering the part by the 5v_supply pin the logic voltage can be as high as the 5v_supply voltage which is typically 5v. logic levels: mute = logic ?0? (low) when 0.5v mute = logic ?1? (high) when 1.4v or floating sel = logic ?0? (low) when 0.5v sel = logic ?1? (high) when 1.4v ac/dc and dir_sel control pins the isl54405 contains c/p (click/pop) shunt circuitry on its com pins (l, r) and on its signal pins (l1, r1, l2, r2). the activation of this circuitry and whether it is located on the com or signal side of the swit ch is determined by the logic levels applied at the ac/dc and dir_sel pins. the dir_sel control pin is only active when ac/dc is logic ?1?. note: any activated c/p shunt ci rcuitry is on when in the mute state (mute = logic ?1?) and off in the audio state (mute = logic ?0?). when ac/dc is logic ?0?, all of the c/p shunt circuitry on both sides of the switch is deactivated and not operable. when ac/dc is logic ?1? then the dir_sel logic level determines whether the shunt circuitry will be activated on the com side of the switch or on the signal side of the switch. when dir_sel = logic ?1? the c/p shunts on the table 2. signal ramp-rate load change with cap ss capacitor value ramp rate turn-on time no capacitor 6250v/s 65s 0.05f 10.3v/s 30ms 0.1f 4.6v/s 58ms isl54405
11 fn6699.1 june 5, 2008 com side (l,r) are activated and inoperable on the signal side (l1, r1, l2, r2) of the switch. when dir_sel = logic ?0? the c/p shunts are activated on the signal side (l1, r1, l2, r2) and inoperable on the com side (l, r). logic levels: ac/dc, dir_sel = logic ?0? (low) when 0.5v ac/dc, dir_sel = logic ?1? (high) when 1.4v or floating. the ac/dc and dir_sel have internal pull-up resistors to the internal 3.3v supply rail and can be driven high or tri-stated (floated by the proce ssor). they should be driven to ground for a logic ?0? (low). note: for 5v applications, the ac/dc and dir_sel pins should never be driven to the external 5v rail. they need to be driven with 1.8v logic or 3v logic circuit. ac coupled or dc coupled operation the audio codec drivers can be directly coupled to the isl54405 when the audio signals from the drivers are ground referenced or do not have a significant dc offset voltage, < 50mv. otherwise the signal should be ac coupled to the isl54405 part. click and pop operation the isl54405 has special circuitry to eliminate click and pops in the speakers during power-up and power-down of the audio codec drivers and during removal and insertion of headphones. a different click and pop scheme is required depending on whether the audio codec drivers are ac coupled or dc coupled to the inputs of the isl54405 part. ac coupled click and pop operation single supply audio drivers have their signal biased at a dc offset voltage, usually at 1/2 the dc supply voltage of the driver. as this dc bias voltage comes up or goes down during power up or down of the driver a transient can be coupled into the speaker load through the dc blocking capacitor (see the ?application block diagrams? on page 8). when a driver is off and suddenly turned on the rapidly changing dc bias voltage at the output of the driver will cause an equal voltage at the in put side of the switch due to the fact that the voltage across the blocking capacitor cannot change instantly. if the switch is in audio mode or there is no low impedance path to discharge the capacitor voltage at the input of the switch, before turn ing on the switch, a transient discharge will occur in the speaker, generating a click and pop noise. proper elimination of a click/ pop transient at the speaker load while powering up or down of the audio driver requires that the isl54405 have its c/p shunts activated on the source side of the switch and then placed in mute mode. this allows the transient gener ated by the audio drivers to be discharged through the click and pop shunt circuitry. once the driver dc bias has reached vdd/2 and the transient on the switch side of the dc blocking capacitor has been discharged to ground through the c/p shunt circuitry, the switches can be turned on and connected through to the speaker loads without generating an undesirable click/pop in the speakers. with a typical dc blocking capacitor of 220f and the c/p shunt circuitry designed to have a resistance of 40 , allowing a 100ms wait time to discharge the transient before placing the switch in the audio mode will prevent the transient from getting through to the speaker load. see figures 25 and 26 in the ?typical performance curves? beginning on page 13. dc coupled click and pop operation the isl54405 can pass ground referenced audio signals which allows it to be directly connected to audio drivers that output ground referenced audio signals, eliminating the need for a dc blocking capacitor. audio drivers that swing around ground however do generate some dc offset, from a few millivolts to tens of millivolts. when switching between audio channels or muting the audio signal these small dc offset levels of the drivers can generate a transient that can cause un-wanted clicks and pops in the speaker loads. in a dc coupled application the c/ p shunt resistors placed at the source side of the switch ha ve no effect in eliminating the transients at the speaker loads when transitioning in and out of the mute state or switching between channels. in fact having these c/p shunts active on the source side only increase un-neccesary power consumption. so, for dc coupled connection the c/p shunt circuitry should not be applied at the source (driver) side of the switch. for dc coupled applications the isl54405 has a special soft-start feature that slowly ramps the dc offset voltage from the audio driver to the speaker load when turning on a switch channel. the ramp rate at the load is determined by the capacitor value connected at the cap_ss pin. lab experimentation has shown that if you can slow the voltage ramp rate at the speaker to < 10v/s, you can eliminate click/pop noise in a speaker. a soft-start capacitor value of 0.1f provides for 4.5v/s ramp rate and is recommended. see figures 27 and 28 in the ?typical performance curves? beginning on page 13. see ?mute to on? section on page 10 for more detail of how soft-start works. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes or diode stacks from the pin to v dd and to gnd (see figure 8). to prevent forward biasing these isl54405
12 fn6699.1 june 5, 2008 diodes, v dd must be applied before any input signals, and the signal voltages must remain between v dd and -3v and the logic voltage must remain between v dd and ground. if these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the foll owing two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin goes below ground by more than -3v or above the v dd rail and the logic pin goes below ground or above the v dd rail. logic inputs can be protected by adding a 1k resistor in series with the logic input (see figure 8). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting schottky diodes to the signal pins (as shown in figure 8) will shunt the fault current to the supply or to ground thereby protecting the switch. these schottky diodes must be sized to handle the expected fault current and to clamp when the voltage reaches the overvoltage limit. . high-frequency performance in 50 systems, the isl54405 has a -3db bandwidth of 230mhz (see figure 29). the frequency response is very consistent over varying analog signal levels. an off-switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off-isolation is the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough from one switch to another. figure 30 details the high off-isolation and crosstalk rejection provided by this part. at 1mhz, off-isolation is about 100db in 50 systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off-isolation and crosstalk rejection due to the voltage divider action of the switch off impedance and the load impedance. figure 8. overvoltage protection gnd v com v nx v dd logic optional protection resistor optional schottky diode optional schottky diode input isl54405
13 fn6699.1 june 5, 2008 typical performance curves t a = +25c, unless otherwise specified figure 9. on-resistance vs switch voltage figure 10. off-isolation, 2v rms signal, 20k load figure 11. off-isolation, 0.707v rms signal, 32 load figure 12. channel-to-channel crosstalk figure 13. channel-to-channel crosstalk f igure 14. insertion loss vs frequency r on ( ) v com (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 -3 -2 -1 0 1 2 3 +85 c +25 c -40 c v dd = 3.3v i com = 80ma frequency (hz) off- isolation (db) 170 80 160 150 140 130 120 110 100 90 20 20k 50 100 200 500 1k 2k 5k 10k no c/p shunt c/p shunt on load side r load = 20k vsignal = 2v rms v dd = 3.3v or v_supply = 5v c/p shunt on signal side 180 80 170 160 150 140 130 120 110 100 90 20 20k 50 100 200 500 1k 2k 5k 10k off- isolation (db) frequency (hz) c/p shunt on signal side no c/p shunt c/p shunt on load side v dd = 3.3v or v_supply = 5v r load = 32 vsignal = 0.707v rms -170 -80 -165 -160 -155 -150 -145 -140 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) crosstalk (db) v dd = 3.3v r load = 20k vsignal = 2v rms frequency (hz) cross talk (db) -150 -80 -145 -140 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 20 20k 50 100 200 500 1k 2k 5k 10k v dd = 3.3v r load = 32 vsignal = 0.707v rms frequency (hz) insertion loss (db) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 20 100 1k 10k 20k v dd = 3.3v r load = 20k v signal = 2v rms isl54405
14 fn6699.1 june 5, 2008 figure 15. gain vs frequency figure 16. stereo imbalance vs frequency figure 17. thd+n vs sig nal levels vs frequency figure 18. thd+n vs signal levels vs frequency figure 19. thd+n vs signal level s vs frequency figure 20. thd+n vs signal levels vs frequency typical performance curves t a = +25c, unless otherwise specified (continued) frequency (hz) gf (db) -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 20 100 1k 10k 20k v dd = 3.3v r load = 20k vsignal = 2v rms relative to 1khz frequency (hz) stereo impbalnce (db) -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 20 100 1k 10k 20k v dd = 3.3v r load = 20k vsignal = 2v rms l2 and r2 l1 and r1 thd+n (%) frequency (hz) -120 -90 -118 -116 -114 -112 -110 -108 -106 -104 -102 -100 -98 -96 -94 -92 20 20k 50 100 200 500 1k 2k 5k 10k r load = 32 a-weighted filter v dd = 3.3v 1v p-p 510mv p-p thd+n (%) frequency (hz) 0.0001 0.0020 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 0.0009 0.0010 20 20k 50 100 200 500 1k 2k 5k 10k r load = 32 a-weighted filter v dd = 3.3v 1v p-p 510mv p-p thd+n( db) frequency (hz) -120 -100 -119 -118 -117 -116 -115 -114 -113 -112 -111 -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 20 20k 50 100 200 500 1k 2k 5k 10k r load = 20k a-weighted filter 2v rms 1.9v rms 1.8v rms 1.5v rms v dd = 3.3v thd+n ( % ) frequency (hz) 0.0001 0.0010 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 0.0009 20 20k 50 100 200 500 1k 2k 5k 10k 2v rms 1.8v rms 1.9v rms 1.5v rms r load = 20k a-weighted filter v dd = 3.3v isl54405
15 fn6699.1 june 5, 2008 figure 21. thd+n vs signal level s vs frequency figure 22. thd+n vs signal levels vs frequency figure 23. psrr vs frequency figure 24. psrr vs frequency figure 25. 20k ac coupled click/pop reduction figure 26. 32 ac coupled click/pop reduction typical performance curves t a = +25c, unless otherwise specified (continued) thd+n( db) frequency (hz) -120 -100 -119 -118 -117 -116 -115 -114 -113 -112 -111 -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 20 20k 50 100 200 500 1k 2k 5k 10k r load = 20k 10hz to 30k filter 2v rms 1.9v rms 1.7v rms to 1.8v rms 1.6v rms 1.5v rms v dd = 3.3v thd+n (%) frequency (hz) 0.00010 0.00100 0.00015 0.00020 0.00025 0.00030 0.00035 0.00040 0.00045 0.00050 0.00055 0.00060 0.00065 0.00070 0.00075 0.00080 0.00085 0.00090 0.00095 20 20k 50 100 200 500 1k 2k 5k 10k r load = 20k 10hz to 30k filter 2v rms 1.9v rms 1.7v rms to 1.8v rms 1.6v rms 1.5v rms v dd = 3.3v psrr ( db) -140 -60 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 20 40k 50 100 200 500 1k 2k 5k 10k 20k v dd = 3.3vdc + 100mv rms signal r load = 20k or 32 audio mode mute mode inputs grounded (c/p shunt on loadside) frequency (hz) psrr (db) frequency (hz) -140 -50 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 20 40k 50 100 200 500 1k 2k 5k 10k 20k 5v_supply = 5vdc + 100mv rms signal r load = 20k or 32 inputs grounded audio mode mute mode (c/p shunt on loadside) time (s) 100ms/div voltage (v) -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 mute 2v/div vdd/2 2v/div l in 200mv/div l out 200mv/div time (s) 100ms/div voltage (v) -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 mute 2v/div l in 200mv/div l out 200mv/div vdd/2 2v/div isl54405
16 fn6699.1 june 5, 2008 figure 27. soft-start (0.1f) click/pop reduction figure 28. soft-start (0.05f) click/pop reduction figure 29. frequency response figure 30. crosstalk and off-isolation die characteristics substrate potential (powered up): gnd transistor count: 3376 process: submicron cmos typical performance curves t a = +25c, unless otherwise specified (continued) time (ms) voltage (mv) -80 -60 -40 -20 0 20 40 60 80 -100 -80 -60 -40 -20 0 20 40 60 80 100 4.6v/s 4.6v/s left input left output right output right input v dd = 3.3v cap_ss = 0.1f time (ms) voltage (mv) -80 -60 -40 -20 0 20 40 60 80 -100 -80 -60 -40 -20 0 20 40 60 80 100 10.3v/s 10.3v/s left input left output right output v dd = 3.3v cap_ss = 0.05f right input frequency (mhz) -3 -1 -2 normalized gain (db) 110100300 0 v dd = 3.3v r load = 50 frequency (hz) off-isolation (db) 120 100 80 60 40 20 0 1k 10k 100k 1m 10m 100m 500m isolation crosstalk -120 -100 -80 -60 -40 -20 0 crosstalk (db) v dd = 3.3v r load = 50 isl54405
17 fn6699.1 june 5, 2008 isl54405 thin shrink small outlin e plastic packages (tssop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ab, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. (angles in degrees) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 0.05(0.002) m16.173 16 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.043 - 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - d 0.193 0.201 4.90 5.10 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.020 0.028 0.50 0.70 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 2/02
18 fn6699.1 june 5, 2008 isl54405 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view bottom view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x e l1 nx l 2 1 0.10 m c a b 0.05 m c 5 nx b (datum b) (datum a) pin #1 id 16x 3.00 1.40 2.20 0.40 0.50 0.20 0.40 0.20 0.90 1.40 1.80 land pattern 10 l16.2.6x1.8a 16 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.55 2.60 2.65 - e 1.75 1.80 1.85 - e 0.40 bsc - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n162 nd 4 3 ne 4 3 0- 12 4 rev. 4 8/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6699.1 june 5, 2008 isl54405 thin quad flat no-lead plastic package (tqfn) thin micro lead frame pl astic package (tmlfp) ) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l16.3x3a 16 lead thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a2 - - 0.80 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 1.35 1.50 1.65 7, 8, 10 e 3.00 bsc - e1 2.75 bsc 9 e2 1.35 1.50 1.65 7, 8, 10 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. compliant to jedec mo-220weed-2 issue c, except for the e2 and d2 max dimension.

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